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1 multimedia ics ntsc / pal digital rgb encoder bu1425ak / BU1425AKV the bu1425ak / BU1425AKV are ics which convert digital rgb / yuv input to composite (ntsc / pal / pal60), luminance (y), and chrominance (c) signals, and outputs the results. applications video interfaces for video-cds and cd-g decoders features 1) input clocks supported 27.0 / 13.5mhz 28.636 / 14.318mhz 28.375 / 14.1875mhz 35.4695 / 17.73475mhz 2) 24-bit rgb and 16-bit yuv input signals are sup- ported. 3) both master and slave systems are supported. 4) 9-bit high-speed dac is used for dac output of composite video, y, and c signals. 5) internal 8-color osd output function is provided. 6) fsc-trap on the y channel can be turned on and off. 7) c channel is equipped with an internal chromi- nance band-pass filter in addition to the u.v. low- pass filter. 8) 5v single power supply, low power consumption (0.4w typ.) 9) y and c output can be turned off (the power con- sumption with y and c off is 0.25w typ.). 10) in the master mode, applying 3.3v to the i / o v dd and 5.0v to other v dd s produces hsy and vsy output with an amplitude of 3.3v. this enables direct connection to lsis that use a power supply voltage of 3.3v. (the clock output for the osd has a fixed amplitude of 5.0v.) 11) in the slave mode, applying voltage to the i / o v dd only, and applying 0v to other v dd s, enables a cur- rent consumption of 0 even when rgb data, hsy, vsy, and osd data are in the active state.
2 multimedia ics bu1425ak / BU1425AKV block diagram bosd gosd rosd osdsw osd palette rgb 24bits y-filter mix sig and sync burst dac v y c c-filter y-level adj chroma gen uv filter latch rd gd / y bd / uv vclk rstb video timing control sync blank burst sub carrier burst generator mode control field / flame control vout yout cout pixclk hsy vsy rgb to yuv test12 addh int im [0.1] yfilonb [1.0] cdgswb pal60b ntb clksw
3 multimedia ics bu1425ak / BU1425AKV pin descriptions pin no. pin name function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 * with pull-down resistor (approx. 30k w ) * bosd gd0 / y0 gd1 / y1 gd2 / y2 gd3 / y3 gd4 / y4 gd5 / y5 gd6 / y6 gnd gd7 / y7 bd0 / uv0 bd1 / uv1 bd2 / uv2 bd3 / uv3 osdsw cdgswb bd4 / uv4 bd5 / uv5 bd6 / uv6 bd7 / uv7 gnd ntb im0 im1 test1 test2 vsy hsy pixclk v dd iov dd int 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 slabeb addh vref-c cgnd cout vgnd vout av ss p-v dd ir av dd ygnd yout v dd yfilon2b ycoff yfilon1b pal60b vclk rstb clksw rd0 rd1 rd2 rosd rd3 rd4 rd5 iov dd rd6 rd7 gosd osd blue data input green data bit0 (lsb) green data bit1 green data bit2 green data bit3 green data bit4 green data bit5 green data bit6 digital ground green data bit7 (msb) blue data bit0 (lsb) blue data bit1 blue data bit2 blue data bit3 osd enable / disable select video-cd / cd-g blue data bit4 blue data bit5 blue data bit6 blue data bit7 (msb) digital ground select ntsc / pal mode select yuv / rgb select dac / normal normally pull down to gnd select u / v timing v-sync input or output h-sync input or output 1 / 2freq. of bclk digital v dd v dd for i / o interlace / non-interlace pin no. pin name select master / slave + 0.5 / 0.5line at non-inter dac bias chroma output ground chroma output composite output ground composite output analog ground (dac vref) power (dac) v dd reference resistor analog (vref) v dd luminance output ground luminance output digital v dd y-filsel throu / filon2 dac (youtcout) off y-filsel throu / filon1 normal / pal60 at palmode video clock input normal / reset sel 1clk / 2clk red data bit0 (lsb) red data bit1 red data bit2 osd red data input red data bit3 red data bit4 red data bit5 v dd for i / o red data bit6 red data bit7 osdgreen data input function
4 multimedia ics bu1425ak / BU1425AKV absolute maximum ratings (ta = 25?) parameter symbol limits unit applied voltage input voltage storage temperature power dissipation v dd , av dd v in tstg pd ?0.5 ~ + 7.0 ?0.3 ~ iov dd + 0.3 ?55 ~ + 150 1350 * 1 v v c mw * 1 reduced by 11mw for each increase in ta of 1 c over 25 c. * 1 when mounted on 120mm 140mm 1.0mm glass epoxy board. * operation is not guaranteed at this value. s not designed for radiation resistance. recommended operating conditions parameter symbol limits unit power supply voltage power supply voltage input high level voltage input low level voltage analog input voltage operating temperature v dd = av dd * iov dd v ih v il v ain topr 0 ~ + 0.8 0 ~ av dd 25 ~ + 60 4.50 ~ 3.30 ~ 2.1 ~ 5.50 5.50 v dd v v v v v c * should be used at v dd = av dd . electrical characteristics (unless otherwise noted, ta = 25?, v dd = av dd = 5.0v, gnd = av ss = vgnd = cgnd = ygnd) parameter symbol min. typ. max. unit conditions digital block ? burst frequency 1 burst frequency 2 burst cycle operating circuit current 1 operating circuit current 2 output high level voltage output low level voltage input high level voltage input low level voltage input high level current input low level current fbst1 fbst2 cbst idd1 idd2 v oh v ol v ih v il i ih i il 4.0 2.1 3.57954 4.43361 9 80 40 4.5 0.5 0.0 0.0 1.0 0.8 10.0 10.0 mhz mhz cyc ma ma v v v v m a m a 27mhz color bar 27mhz color bar pd mode i oh = ?2.0ma i oh = 2.0ma ?10 ?10 dac block ? dac resolution linearity error y white level current y black level current y zero level current v white level current v black level current v zero level current res el iyw iyb iyz iyw iyb iyz 9 25.14 7.24 0.0 25.14 7.24 0.0 10.0 10.0 bits lsb ma ma m a ma ma m a ir = 1.2k w sleep mode current iddpd 1.0 m a v in max. = iov dd + 0.3v v in min. = 0.3v ?10 ?10 0.5 3.0
5 multimedia ics bu1425ak / BU1425AKV application example (1) example in master mode: doubled clock is input and 24-bit rgb input is used 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 65 43210 3 7 6 5 4 6 7 4 3 5 1 0 2 210 b data 0...7 g data 0...7 r data 0...7 [blue] [green] [red] osd in vsync out hsync out osd clock 75 75 75 osd in osd in video-cd / cd-g 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 reset [low active] in pixel clock in y-filter select interlace / non-inter pal / ntsc digital gnd chrominance composite luminance main v dd 5.0 v sleep mode ctl l: sleep h: normal i / o v dd 5.0v or 3.3v bu1425ak / akv analog v dd 1.2k 0.01 m f analog gnd power gnd power v dd digital v dd cdgswb osdsw bd3 bd2 bd1 bd0 gd7 gnd gd6 gd5 gd4 gd3 gd2 gd1 gd0 bosd slabeb addh vref cgnd cout vgnd v out av ss av dd ir av dd ygnd yout v dd yfilon2b ycoff bd4 bd5 bd6 bd7 gnd ntb im0 im1 test1 test2 vsy hsy pixclk v dd i / o v dd int gosd rd7 rd6 i / o v dd rd5 rd4 rd3 rosd rd2 rd1 rd0 clksw rstb vclk pal gob yfilon1b osd enable fig.1
6 multimedia ics bu1425ak / BU1425AKV (2) example in slave mode: doubled clock is input and 16-bit yuv input is used 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 65 43210 3 7 6 5 4 6 7 4 3 5 1 0 2 210 u.v data 0...7 y data 0...7 [blue] [green] [red] osd in osd clock 75 75 75 osd in osd in video-cd / cd-g 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 reset [low active] in pixel clock in y-filter select interlace / non-inter pal / ntsc digital gnd hsync in vsync in chrominance composite luminance main v dd 5.0v sleep mode ctl l: sleep h: normal i / 0 v dd 5.0v or 3.3v bu1425ak / akv analog vdd 0.01 m f analog gnd power gnd power vdd digital vdd cdgswb osdsw bd3 bd2 bd1 bd0 gd7 gnd gd6 gd5 gd4 gd3 gd2 gd1 gd0 bosd slabeb addh vref cgnd cout vgnd v out av ss av dd ir av dd ygnd yout v dd yfilon2b ycoff bd4 bd5 bd6 bd7 gnd ntb im0 im1 test1 test2 vsy hsy pixclk v dd i / o v dd int gosd rd7 rd6 i / o v dd rd5 rd4 rd3 rosd rd2 rd1 rd0 clksw rstb yclk pal gob yfilon1b 1.2k fig.2 osd enable
7 multimedia ics bu1425ak / BU1425AKV equivalent circuits pin no. pin name equivalent circuit i / o function 2 ~ 8 10 gd (7: 0) g data input pin for 24-bit rgb input y data input pin for 16-bit yuv input 11 ~ 14 17 ~ 20 bd (0: 7) b data input pin for 24-bit rgb input u, v data input pins for 16-bit yuv input control pins used to select rgb (24- bit), yuv (16-bit) or dac through as the input mode. 16 cdgswb switches the mode between video- cd (high) and cd-g (low). 54 ~ 56 58 ~ 60 62.63 rd (0: 7) r data input pin for 24-bit rgb input 1 57 64 15 rosd gosd bosd osdsw osd data input pin when using the osd function. when the osdsw pin is high, input to the rosd, gosd, and bosd pins takes precedence over rgb, and the data is converted. 23 24 im0 im1 22 ntb switches the mode between ntsc (low) and pal (high). i i i i i i i
8 multimedia ics bu1425ak / BU1425AKV pin no. pin name equivalent circuit i / o function 27 vsy i / o vertical synchronization signals (vsync) are input (when slabeb = low) or output (when slabeb = high) here. 35 vref-c i this is the reference voltage generator circuit monitoring pin which deter- mines the output amplitude (output cur- rent for 1 lsb) of the dac. a 0.01 m f capacitor should be attached between this and pin 43 (av dd ). 29 pixclk o the internal processing clock is divid- ed in half and output. data is read at the point at which the edge of this clock changes. this can also be used as the clock for the osd ic. 32 int i this pin switches between interlace (when high) and non-interlace (when low) modes. this pin is effective in both the video-cd and cd-g modes. 33 34 slabeb addh i i this pin switches between the master (when high) and slave (when low) modes. it is effective in the non- interlace mode, and it switches bet- ween 0.5 lines (when low) and + 0.5 lines (when high) for the number of lines in an interlace field. 28 hsy i / o this is the horizontal synchronization signal pin. negative polarity hsync signals are input (when slabeb = low) or output (when slabeb = high) here. this is also used as the synchronization signal for fixing the pixclk output phase. 37 cout o this is the chrominance output pin for the s pin.
9 multimedia ics bu1425ak / BU1425AKV pin no. pin name equivalent circuit i / o function 39 vout o composite output pin 45 yout o luminance output pin for the s pin 42 ir i the output amplitude (output current for 1 lsb) of the dac is specified using an external resistor, and this pin controls the value of the current flow- ing per bit. 48 ycoff i when there is high input at the signal input pin which switches to and from the low power consumption mode, this turns off the output from the yout and cout pins. 51 49 vclk input pin for the reference clock in the video-cd mode 52 rstb reset input pin which initializes the system. the system is reset when this goes low. yfilon1b yfilon2b selects the f characteristic of the y-filter. i i i
10 multimedia ics bu1425ak / BU1425AKV pin no. pin name equivalent circuit i / o function 53 clksw i 50 pal60b switches between the pal and pal60 modes. this is effective only when the ntb pin is high. (pal mode only) this switches between dividing the vclk input in half and using it as an internal clock (when low), and using it as an internal clock without dividing it in half (when high). 25 26 test1 test2 i normally, this is connected to the gnd pin. however, when 16-bit yuv input is used, the test2 pin can be used as the u and v timing control pins. i 31 46 61 41 43 av dd iov dd power supply pin for the digital, the analog, and i / o blocks 9 21 36 38 40 44 gnd cgnd vgnd av ss ygnd grounding pin for the digital and analog blocks 30 v dd digital v dd . equipped with pull-down resistor.
11 multimedia ics bu1425ak / BU1425AKV circuit operation table 1: low power consumption mode with the ycoff pin pin no. pin name ycoff low high vout pin composite signal composite signal 48 output mode and power consumption yout pin luminance signal no output (0v) cout pin chrominance signal no output (0v) power consumption (typ.) 0.45w 0.25w (1) overview the bu1425ak / akv converts digital images and video data with an 8-bit configuration to 9-bit composite signals (v out ), luminance signals (yout), and chrominance sig- nals (cout) for the ntsc, pal, and pal60 formats, and outputs the converted data as analog tv signals. the user may select whether v out consists of chromi- nance signals that have passed through a chrominance band pass and luminance signals that have been mixed, or luminance signals that have passed through a chromi- nance trap and luminance signals that have not passed through a chrominance trap. the f characteristic of this chrominance trap may be selected from among three available types. since yout normally does not pass through the trap, it is optimum for the s pin. cout nor- mally passes through the chrominance band pass, and is thus highly resistance to dot interference. in addition, when used in the doubled clock mode, it passes through an interpolator filter, and for that reason is able to repro- duce even cleaner image quality. a correspondence can be set up between input digital image data and video-cd and cd-g decoder output. output tv signals, in addition to switching among the ntsc, pal, and pal60 modes, can be switched between the interlace and non-interlace modes. the data clock input to the vclk pin can also be input as a doubled clock for the data rate (in doubled clock modes). in doubled clock modes, data is read and processed at the rising edge of an internal clock that has been divided in half. in ordinary clock modes, data is read and processed at the rising edge of the clock that has the same phase as the input clock. two input data formats are supported: 24-bit rgb (4: 4: 4) and 16-bit yuv (4: 2: 2). these are input to rd0 to 7, gd0 to 7, and bd0 to 7, respectively. the selected input format can be switched using the im0 and im1 pin input. when the osdsw pin is set to the "enabled" (h) state, data input to the rosd, gosd, and bosd pins becomes effective, making it possible to input 7-color (8 including black) chrominance data. at the same time, a clock with a fre- quency half that of the internal clock is output from the pixclk pin. as a result, the pixclk pin can easily be directly connected to the osd ic clock input pin, and the osdsw pin can be directly connected to the blk output pin. thus, the bu1425ak and the osd ic can be syn- chronized, and osd text with a burster trimmer stacker feature can be used. if the input data is in the rgb format, it is converted to yuv. if it is in the yuv format, it is converted from the ccir-601 format to level-shifted yuv data. the yuv data is then adjusted to the 100ire level in the ntsc, pal, and pal60 modes, and u and v data is phase- adjusted by a sub-carrier generated internally, and is modulated to chrominance signals. ultimately, elements such as the necessary synchroniza- tion level, the color blanking level, and burst signals are mixed, and pass through the 9-bit dac to be output as ntsc or pal composite signals, luminance signals, and chrominance signals (conforming to rs-170a). at this point, the dac is operating at twice the internal clock, making it possible to reduce the number of attachments. furthermore, luminance signal output and chrominance signal output can be turned off. at this point, it is possible to reduce the level of power consumption. the dac output is current output. if a resistor of a speci- fied value is connected to the ir pin, 2.0v p-p output can be obtained by connecting 75 w to the vout pin as an external resistor. as a result, normally, when a video input pin (75 w terminus) is connected, the output is approximately 1.0v p-p voltage output at a white 100% level. (2) specifying the mode 1) power saving mode with the bu1425ak / akv, setting the ycoff pin to high turns off the output from the yout and cout pins of the dac output, enabling use in the low power con- sumption mode.
12 multimedia ics bu1425ak / BU1425AKV 2) output modes the ?ideo-cd?and ?d-g?modes can be supported by both digital image and video data, with the mode being switched by the cdgswb pin input. when the cdgswb pin input is low, the cd-g mode is set, and when high, the video-cd mode is set. also, the ?tsc? ?al? and ?al60?modes may be selected as the output tv modes. the output tv mode is switched using the ntb and pal60 pin input. setting the ntb pin input to low sets the ntsc mode, and setting it high with the pal60 pin also high sets the pal mode. setting the ntb pin high and the pal60 pin low, sets the pal60 mode. table 2: specifying modes ntb pal60 * * 0 0 1 1 cdgswb 0 1 0 1 0 1 decoder mode cd-g video-cd cd-g video-cd cd-g video-cd 0 0 1 1 1 1 tv mode ntsc ntsc pal60 pal60 pal pal also, int pin input can be used to switch between ?nterlace output?and ?on-interlace output. setting the input to low enables non-interlace output, and setting it to high enables interlace output. when non-interlace output is used, the number of lines in one field can be controlled using the addh pin. if the addh pin is low, the number of lines in one field is set to the number of interlace output lines minus 0.5 lines, and when high, the number of lines in one field is set to the number of interlace output lines plus 0.5 lines. table 3: pin settings for interlace / non-interlace modes int a dd h scan mode no. of lines / field 0 1 * non-interlace non-interlace interlace 262 263 262.5 312 313 312.5 0 0 1 ntsc / pal60 pal 3) input formats the digital data input format can be set as shown in the table below, using the im1 and im0 pins. both 24-bit rgb (4: 4: 4) and 16-bit yuv (4: 2: 2) are supported. in addition, digital rgb input can be output as analog rgb output (rgb through mode). table 4: input format settings im1 im0 0 1 0 1 input format r (8 bits), g (8 bits), b (8 bits) 16-bit yuv (4: 2: 2) rosd, gosd, bosd expanded to rgb input output signal tv signals (9-bit resolution) tv signals (9-bit resolution) rgb analog signals (9 bits) 0 0 1 1
13 multimedia ics bu1425ak / BU1425AKV table 5: bit assignments in rgb through mode output pin yout (45) vout (39) cout (37) bit8 rd7 gd7 bd7 bit7 rd6 gd6 bd6 bit6 rd5 gd5 bd5 bit5 rd4 gd4 bd4 bit4 rd3 gd3 bd3 bit3 rd2 gd2 bd2 bit2 rd1 gd1 bd1 bit1 rd0 gd0 bd0 bit0 rosd gosd bosd the bu1425ak / akv has an internal osd switch and chrominance data generating function. consequently, joint usage of an osd-ic with blanking and r, g, and b output can be easily supported by the osd. moreover, a clock with half the internal processing frequency of the bu1425ak is output from the pixclk pin, and can be connected to the osd-ic clock input, enabling the timing to be captured. rosd, gosd, and bosd pin input is effective as long as the osdsw pin input is high. the relationship between osd data and chrominance data is as shown in table 6 below. table 6: correspondence between osd function, input data and chrominance output osdsw rosd 0 0 0 0 1 1 1 1 * gosd 0 0 1 1 0 0 1 1 * bosd 0 1 0 1 0 1 0 1 * 1 1 1 1 1 1 1 1 0 output chrominance signal black (blanking) blue green cyan red magenta yellow white based on input specified by im0 and im1 4) clock modes with the bu1425ak / akv, clock input is available at the vclk pin. clocks supplied from an external source should basically be input at a frequency double that of clocks used inter- nally (basic clock: bclk) (when the clksw pin is low). the phase relationship between the internal clock and the external clock at this time is as shown in fig. 3, with the hsy pin input serving as a reference. in the master mode, in which data from the hsy pin is output and used, hsy is output at the timing shown in fig. 3. with the bu1425ak, data (rd, gd, bd, etc.) is read at the ris- ing edge of the internal clock (bclk), so data should be input to the bu1425ak / akv as shown in fig. 3. hsy vclk internal clock (bclk) input data fig. 3 illustration of clock timing (clksw is low)
14 multimedia ics bu1425ak / BU1425AKV also, setting the clksw pin to high enables the fre- quency of the external clock to be used as bclk, the internal clock, just as it is. since the data is read to the bu1425ak / akv at the rising edge of bclk at this time as well, data should be input as shown in fig. 4. the relationship with hsy is also as shown in fig. 4. hsy vclk internal clock (bclk) input data fig. 4 illustration of clock timing (clksw is high) with the bu1425ak / akv, the sub-carrier (burst) fre- quency is generated using the internal clock. for this reason, the frequencies used in the various modes are limited, so those frequencies should be input (see table 7 below). table 7: bu1425ak / akv clock input frequency settings clksw pin video-cd mode 27.000mhz 13.500mhz cd-g mode same for ntsc / pal / pal60 ntsc 28.636mhz 14.318mhz 0 1 pal / pal60 28.3750mhz 14.1875mhz 5) synchronization signals the bu1425ak / akv has an "encoder master" mode in which synchronization signals are output, and an "encoder slave" mode in which synchronization signals are input from an external source and used to achieve synchronization. these modes are switched at the slabeb pin. when the slabeb pin is low, the slave mode is in effect, and when high, the master mode is in effect. in the master mode, the hsy and vsy pins serve as out- put, with horizontal synchronization signals (hsync) being output from the hsy pin and vertical synchroniza- tion signals (vsync) from the vsy pin. at this time, the reference timing for synchronization signal output is determined at the rising edge of the rstb pin. output is obtained in accordance with the specified mode (ntsc, pal, or pal60, interlace or non-interlace). output in the non-interlace mode, however, is output only under "odd" field conditions (the falling edges of hsy and vsy are the same). in the slave mode, the hsy and vsy pins serve as input, and horizontal synchronization signals (hsync) should be input to the hsy pin and vertical synchronization sig- nals (vsync) to the vsy pin. the input synchronization signals at this time should be input in accordance with the specified mode. with the bu1425ak / akv, field dis- tinction between odd and even fields is made automati- cally for each field when interlace input is used. with the bu1425ak, all synchronization signals are treated as negative polarity signals (signals for which the sync inter- val goes low). when using the non-interlace mode, operation is normally carried out under odd field condi- tions (the falling edges of hsy and vsy are simultane- ous).
15 multimedia ics bu1425ak / BU1425AKV 6) y filter with the bu1425ak / akv, the frequency characteristic of y, which is mixed with the vout pin output, is set so that it can be selected using the yfilon1b and 2b pins. a through filter is normally used on the yout pin output, so that it is not limited to this method. table 8: frequency characteristic of the y channel yfilon2b yfilon1b h trap filter through (same signal as yout pin output is mixed with vout) frequency characteristic of the y channel chart1 chart2 chart3 h h l l l h l 100 ?0 10 20000 10000 1000 amplitude (db) phase (deg) frequency (khz) 5 0 ? ?0 ?5 ?20 ?25 ?30 ?35 90 45 0 180 135 ?45 ?0 135 ?180 gain-phase graphic fig.5 chart1 (bclk = 13.5mhz) 100 ?0 10 20000 10000 1000 amplitude (db) frequency (khz) 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 phase (deg) 90 45 0 180 135 ?5 ?90 135 180 gain-phase graphic fig.6 chart2 (bclk = 13.5mhz) 100 ?0 10 20000 10000 1000 amplitude (db) frequency (khz) 5 0 ? ?0 ?5 ?0 ?5 ?0 ?5 phase (deg) 90 45 0 180 135 ?5 ?0 135 180 gain-phase graphic fig.7 chart3 (bclk = 14.318mhz)
16 multimedia ics bu1425ak / BU1425AKV (3) output level figures 8 to 10 indicate the digital data values for the dac output when the color bars from the various pins are reproduced. white yellow cyan green magen red blue black black level = pedestal level sync tip level fig. 8 yout output b l a c k w h i t e y e l l o w c y a n g r e e n m a g e n t a r e d b l u e color burst black level fig. 9 cout output black level = pedestal level sync tip level y e l l o w c y a n g r e e n m a g e n t a r e d b l u e b l a c k w h i t e fig. 10 vout output
17 multimedia ics bu1425ak / BU1425AKV table 9: bu1425ak color bar input / output data rd 00 00 00 00 ff ff ff ff sync tip color burst ntsc color burst pal blank level black (pedestal) blue green cyan red magenta yellow white rgb24bit yout gd 00 00 ff ff 00 00 ff ff bd 00 ff 00 ff 00 ff 00 ff yd 10 28 90 a9 51 6a d2 eb yuv (4: 2: 2) name&color ud 80 f1 36 a5 5a c9 0e 80 input (8-bit hexadecimal for each) output (9-bit hexadecimal for each) vd 80 6d 22 10 f0 dd 92 80 033 038 072 096 0a0 0a0 096 072 033 038 072 096 0a0 0a0 096 072 000 072 092 117 138 0c6 0e6 16c 18c cout v out * cout and vout display the chrominance amplitude. cout is c8h xxxh. vout is yout xxxh. 000 000 100 072 000 000 (4) timing table 10 below shows the input and output pins related to timing. table 10: bu1425ak timing-related input / output pins pin no. pin name function 52 51 53 27 28 16 22 50 32 33 34 29 rstb vclk clksw vsy hsy cdgswb ntb pal60b int slabeb addh pixclk i / o i i i i / o i / o i i i i i i o system reset input pin clock input pin clock input mode setting pin vertical synchronization signal i / o pin horizontal synchronization signal i / o pin video-cd / cd-g mode switching pin ntsc / pal mode switching pin pal / pal60 mode switching pin interlace / non-interlace mode switching pin master / slave mode switching pin pin which adds 1 line in non-interlace mode 1 / 2 divider output for internal clock (osd clock)
18 multimedia ics bu1425ak / BU1425AKV 1) input clocks and input data timings in the various operation modes there are slight differences in the input data and the clock timing, depending on which mode is being used. what is shared by all modes is that, with the bu1425ak / akv, data is read and discharged at the rising edge of the internal clock. the illustration below shows the input con- ditions in the various modes. 1. master mode, * 1 clock mode encoder master (pin 33 = h) internal clock = input clock (pin 53 = h) input data output data (hsy, vsy) vclk (pin53) tds1 internal clock (bclk) fig.11 * in this mode, the internal clock (bclk) begins to operate at the same phase as the vclk input, following the rise of the rstb pin (pin 52). table 11 parameter symbol max. typ. min. tds1 10 data setup time 1
19 multimedia ics bu1425ak / BU1425AKV 2. master mode, doubled clock mode encoder master (pin 33 = h) internal clock = 2 * input clock (pin 53 = h) input data output data (hsy, vsy) vclk (pin53) tds2 internal clock (bclk) fig.12 * in this mode, the internal clock (bclk) begins to operate at a halved frequency at the rise of the vclk input, fol- lowing the rise of the rstb pin (pin 52). table 12 parameter symbol max. typ. min. tds2 10 data setup time 2 3. slave mode, * 1 clock mode encoder slave (pin 33 = h) internal clock = input clock (pin 53 = h) input data input data (hsy, vsy) vclk (pin53) tds3s internal clock (bclk) tds3h tsh1 tsd1 fig.13
20 multimedia ics bu1425ak / BU1425AKV * in this mode, the internal clock (bclk) begins to operate at the same phase as the vclk input, following the rise of the rstb pin (pin 52). table 13 parameter symbol max. typ. min. tds3s tds3h tsd1 tsh1 5 8 5 8 data setup time 3s data hold time 3h sync signal setup time sync signal hold time 4. slave mode, doubled clock mode encoder slave (pin 33 = l) internal clock = 2 * input clock (pin 53 = l) tsh2 tsd2 input data input data (hsy, vsy) vclk (pin53) tds4 internal clock (bclk) fig.14 * in this mode, the internal clock (bclk) begins to operate at a halved frequency at the rise of the vclk input, fol- lowing the rise of the rstb pin (pin 52). when hsy is input, phase correction is carried out at the falling edge, as shown in fig. 14. (in other words, the phase of the internal clock (bclk) is not determined until hsy is input.) table 14 parameter symbol max. typ. min. tds4 tsh2 tsd2 10 10 10 data setup time 4 sync signal hold time 2 sync signal setup time 2
21 multimedia ics bu1425ak / BU1425AKV 2) clock timing when the osd function is used eight-color osd color with a burster trimmer stacker fea- ture can be used, simply by connecting an osd with external clock input. output from the pixclk pin of the bu1425ak should be input to the osc-in of the osd ic. the osdsw input pin can be used as a signal for the burster trimmer stacker feature called vblk, or a similar name. (see page 13 for a table showing the correspon- dence between input data and color output.) black yellow video-data video-data internal clock (bclk) hsy (in / out) pixclk osdsw rosd.gosd v.y.c.out fig. 15 clock timing with the osd function * the frequency of the pixclk pin output is one-half that of the internal clock. this phase is determined at the rising edge of hsy, as shown in fig.15. (in the encoder master mode, phase correction is implemented using the hsy output of the bu1425ak itself.) the osd function is effective only during the time that video output is enabled. (see the tv signal timing diagram on page 27.)
22 multimedia ics bu1425ak / BU1425AKV 3) output timing 1. master mode, doubled clock mode encoder master (pin 33 = h) internal clock = input clock * 1 / 2 (pin 53 = l) thdf tvdf tpdr vclk internal clock (bclk) hsy (out) vsy (out) pixclk (out) thdr tvdr fig. 16 output timing with a doubled clock table 15 parameter symbol max. typ. min. thdr thdf tvdr tvdf tpdr tpdf 14 14 14 hsy output delay vsy output delay pixclk output delay
23 multimedia ics bu1425ak / BU1425AKV 2. master mode, regular clock mode encoder master (pin 33 = h) internal clock = input clock (pin 53 = l) thdf tvdf tpdr vclk internal clock (bclk) hsy (out) vsy (out) pixclk (out) tvdr thdr fig. 17 output timing with a clock at the regular frequency table 16 parameter symbol max. typ. min. thdr thdf tvdr tvdf tpdr tpdf 10 10 10 hsy output delay vsy output delay pixclk output delay
24 multimedia ics bu1425ak / BU1425AKV 4) odd / even recognition timing in slave mode 1. timing based on recognition of odd conditions the bu1425ak / akv distinguishes whether the condi- tions of each field (each time that vsy is input) are odd or otherwise, and internal operation is carried out based on that recognition after the data is input. as a result, hsy and vsy are input under input conditions appropri- ate to the specified mode, enabling regulated output for the first time. odd input conditions are indicated below. timing that does not match these conditions is recog- nized as an even field. expanded view hsy vsy hsy tvl vsy thvdiff fig. 18 odd recognition conditions table 17: odd recognition conditions vsy delay from hsy parameter symbol max. typ. min. tvl 128 vsy input l interval thvdiff unit bclk bclk hsy rising edge ?2clk hsy falling edge ?1clk * bclk = one cycle of internal clock
25 multimedia ics bu1425ak / BU1425AKV 2. even timing the bu1425ak / akv distinguishes whether the condi- tions of each field (each time that vsy is input) are odd or otherwise, and internal operation is carried out based on that recognition after the data is input. as a result, hsy and vsy are input under input conditions appropri- ate to the specified mode, enabling regulated output for the first time. timing that does not match the odd field conditions is recognized as an even field. in order to pre- vent malfunctioning of the internal hsy counter, howev- er, there are regulations which apply to the timing at which vsync is input in even fields. expanded view hsy vsy hsy t = 1 / fhsync t = 1 / fhsync * 1 / 2 t = 1 / fhsync * 1 / 2 the middle of hsy tvl vsy thvdiff fig. 19 even conditions table 18: even conditions parameter symbol max. typ. min. tvl 128 vsy input l interval thvdiff unit bclk bclk hsy falling edge ?128clk the middle of hys ?128clk vsy delay from the middle of hsy * bclk = one cycle of internal clock
26 multimedia ics bu1425ak / BU1425AKV parameter symbol unit ntsc v-cd pal td1 td2 td3 td4 td5 bclk bclk bclk bclk bclk sync rise burst start burst end data start 1-line interval pal60 cd-g v-cd cdg1 v-cd cdg1 64 71 106 128 858 67 76 112 135 910 64 71 106 142 864 67 75 112 149 908 64 71 106 128 858 67 75 112 135 902 burst vout (39) burst burst burst yout (45) cout (37) td1 td2 td3 td4 td5 fig. 20 tv signal timing diagram table 19
27 multimedia ics bu1425ak / BU1425AKV frame timing in video-cd mode (ntsc / pal60: interlace) 522 523 524 525 odd_field hsync (28pin) vsync (27pin) vout (39pin) 123456789101112 181920 * * indicates a line interval during which video data is output 259 260 261 262 even_field hsync (28pin) vsync (27pin) vout (39pin) 263 264 265 266 267 268 269 270 271 272 273 274 281 282 fig. 21
28 multimedia ics bu1425ak / BU1425AKV frame timing in video-cd mode (pal: interlace) odd_field * 4 hsync (28pin) vsync (27pin) vout (39pin) 623624625123456789101112 232425 * 3 even_field * 4 hsync (28pin) vsync (27pin) vout (39pin) 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 335 336 337 fig.22 * 3 indicates a line interval during which video data is output * 4 first and second have been added to aid in explanation, but there is no actual distinction.
29 multimedia ics bu1425ak / BU1425AKV frame timing in cd-g mode (ntsc / pal60: non-interlace) 521 522 523 524 first_field * 4 hsync (28pin) vsync (27pin) vout (39pin) 123456789101112 181920 * 3 * 3 indicates a line interval during which video data is output * 4 first and second have been added to aid in explanation, but there is no actual distinction. 259 260 261 262 second_field * 4 hsync (28pin) vsync (27pin) vout (39pin) 263 264 265 266 267 268 269 270 271 272 273 274 281 282 fig.23
30 multimedia ics bu1425ak / BU1425AKV frame timing in cd-g mode (pal: non-interlace) hsync (28pin) vsync (27pin) vout (39pin) 622623624123456789101112 232425 * 3 * 3 indicates a line interval during which video data is output * 4 first and second have been added to aid in explanation, but there is no actual distinction. hsync (28pin) vsync (27pin) vout (39pin) 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 335 336 337 first_field * 4 second_field * 4 fig.24
31 multimedia ics bu1425ak / BU1425AKV (5) adjustment of the dac output level the voltage level of the dac output is determined by the dac internal output current and the dac output external resistor. the output current per 1 dac bit is determined by the external resistor of the ir pin (pin 42), as shown below. i (1lsb) = vvref/rir * 1 / 16 [a] ... (equation 6-1) vvref ... voltage generated by the regulator circuit in the bu1425ak [v] rir ... external resistor for the ir pin 1200[ w ] consequently, when vvref = 1.3v and rir = 1200 w , a current of 67.71 m a per 1lsb is output. because the white level of y is a digital value of 396 (decimal value), the following results: v (y white) = 0.0677 396 = 26.81ma at this point, if the dac output external resistance is 37.5 w , an amplitude of 1.005v p-p is obtained. (6) yuv input mode with the bu1425ak, setting the im0 pin (pin 23) to high enables a 16-bit yuv input format to be support- ed. at that time, the timing of u and v can be reversed when data is input, using the h / l state of the test2 pin. the input conditions for this mode are shown below. 0 internal clock (bclk) hsy y-data u.v-data 12 2n y5 y4 y3 y2 y1 u5 v3 u3 v1 u1 2n + 1 fig. 25 yuv input timing when test[2] = l internal clock (bclk) hsy y-data u.v-data 012 2n y5 y4 y3 y2 y1 u5 v3 u3 v1 u1 2n + 1 fig. 26 yuv input timing when test[2] = h
32 multimedia ics bu1425ak / BU1425AKV * reversal of the u and v timing using the h / l state of test[2] can be controlled regardless of whether clksw is high or low (the input clock is a doubled clock or not). * when using the rgb input mode, test[2] should be fixed at low. * in the master mode, hsync is output at the timing shown in fig. 26. for that reason, the timing of u and v should be determined by counting from that falling edge. in the slave mode, the hsy, u, and v data should be input at the timing shown in fig. 26. table 20 test2 (pin26) clksw (pin53) 0 0 1 1 0 1 0 1 in a doubled clock mode, the timing of u and v is as shown in fig. 7-1. in a regular clock mode, the timing of u and v is as shown in fig. 7-1. in a doubled clock mode, the timing of u and v is as shown in fig. 7-2. in a regular clock mode, the timing of u and v is as shown in fig. 7-2. external dimensions (units: mm) vqfp64 qfp-a64 bu1425ak BU1425AKV 0.15 0.1 48 33 32 17 49 64 1 16 14.0 0.2 16.4 0.3 14.0 0.2 0.35 0.1 0.05 0.5 16.4 0.3 0.8 2.7 0.1 0.15 48 33 32 17 16 1 49 64 10.0 0.2 12.0 0.3 10.0 0.2 12.0 0.3 0.2 0.1 0.1 0.5 0.125 0.1 0.5 0.10 1.4 0.1

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